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file:/home/jivera/wd/pcsx/ix86/iGte.h (Tue Nov 25 22:46:14 2003
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1: /* Pcsx - Pc Psx Emulator
2: * Copyright (C) 1999-2003 Pcsx Team
3: *
4: * This program is free software; you can redistribute it and/or modify
5: * it under the terms of the GNU General Public License as published by
6: * the Free Software Foundation; either version 2 of the License, or
7: * (at your option) any later version.
8: *
9: * This program is distributed in the hope that it will be useful,
10: * but WITHOUT ANY WARRANTY; without even the implied warranty of
11: * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12: * GNU General Public License for more details.
13: *
14: * You should have received a copy of the GNU General Public License
15: * along with this program; if not, write to the Free Software
16: * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17: */
18:
19:
20: #define CP2_FUNC(f) \
21: void gte##f(); \
22: static void rec##f() { \
23: iFlushRegs(); \
24: MOV32ItoM((u32)&psxRegs.code, (u32)psxRegs.code); \
25: CALLFunc ((u32)gte##f); \
26: /* branch = 2; */\
27: }
28:
29: #define CP2_FUNCNC(f) \
30: void gte##f(); \
31: static void rec##f() { \
32: iFlushRegs(); \
33: CALLFunc ((u32)gte##f); \
34: /* branch = 2; */\
35: }
36:
37: /*CP2_FUNC(MFC2);
38: CP2_FUNC(MTC2);
39: CP2_FUNC(CFC2);
40: CP2_FUNC(CTC2);
41: CP2_FUNC(LWC2);
42: CP2_FUNC(SWC2);*/
43:
44: void gteMFC2();
45: static void recMFC2() {
46: // Rt = Cop2D->Rd
47: if (!_Rt_) return;
48:
49: iRegs[_Rt_].state = ST_UNK;
50:
51: switch (_Rd_) {
52: case 29:
53: MOV32ItoM((u32)&psxRegs.code, (u32)psxRegs.code);
54: CALLFunc ((u32)gteMFC2);
55: break;
56:
57: default:
58: MOV32MtoR(EAX, (u32)&psxRegs.CP2D.r[_Rd_]);
59: MOV32RtoM((u32)&psxRegs.GPR.r[_Rt_], EAX);
60: break;
61: }
62: }
63:
64: void gteMTC2();
65: static void recMTC2() {
66: // Cop2D->Rd = Rt
67: int fixt = 0;
68:
69: // iFlushRegs();
70:
71: switch (_Rd_) {
72: case 8: case 9: case 10: case 11:
73: fixt = 1; break;
74:
75: case 16: case 17: case 18: case 19:
76: fixt = 2; break;
77:
78: case 15:
79: case 28:
80: case 30:
81: MOV32ItoM((u32)&psxRegs.code, (u32)psxRegs.code);
82: CALLFunc ((u32)gteMTC2);
83: break;
84: }
85:
86: if (IsConst(_Rt_)) {
87: if (fixt == 1) MOV32ItoM((u32)&psxRegs.CP2D.r[_Rd_], (s16)iRegs[_Rt_].k);
88: else if (fixt == 2) MOV32ItoM((u32)&psxRegs.CP2D.r[_Rd_], iRegs[_Rt_].k & 0xffff);
89: else MOV32ItoM((u32)&psxRegs.CP2D.r[_Rd_], iRegs[_Rt_].k);
90: } else {
91: MOV32MtoR(EAX, (u32)&psxRegs.GPR.r[_Rt_]);
92: if (fixt == 1) MOVSX32R16toR(EAX, EAX);
93: else if (fixt == 2) AND32ItoR(EAX, 0xffff);
94: MOV32RtoM((u32)&psxRegs.CP2D.r[_Rd_], EAX);
95: }
96: }
97:
98: void gteLWC2();
99: static void recLWC2() {
100: // Cop2D->Rt = mem[Rs + Im] (unsigned)
101: int fixt = 0;
102:
103: switch (_Rt_) {
104: case 8: case 9: case 10: case 11:
105: fixt = 1; break;
106:
107: case 16: case 17: case 18: case 19:
108: fixt = 2; break;
109:
110: case 15:
111: case 28:
112: case 30:
113: iFlushRegs();
114: MOV32ItoM((u32)&psxRegs.code, (u32)psxRegs.code);
115: CALLFunc ((u32)gteLWC2);
116: return;
117: }
118:
119: if (IsConst(_Rs_)) {
120: u32 addr = iRegs[_Rs_].k + _Imm_;
121: int t = addr >> 16;
122:
123: if ((t & 0x1fe0) == 0) {
124: MOV32MtoR(EAX, (u32)&psxM[addr & 0x1fffff]);
125: if (fixt == 1) MOVSX32R16toR(EAX, EAX);
126: else if (fixt == 2) AND32ItoR(EAX, 0xffff);
127: MOV32RtoM((u32)&psxRegs.CP2D.r[_Rt_], EAX);
128: return;
129: }
130: if (t == 0x1f80 && addr < 0x1f801000) {
131: MOV32MtoR(EAX, (u32)&psxH[addr & 0xfff]);
132: if (fixt == 1) MOVSX32R16toR(EAX, EAX);
133: else if (fixt == 2) AND32ItoR(EAX, 0xffff);
134: MOV32RtoM((u32)&psxRegs.CP2D.r[_Rt_], EAX);
135: return;
136: }
137: }
138:
139: iPushOfB();
140: CALLFunc((u32)psxMemRead32);
141: if (fixt == 1) MOVSX32R16toR(EAX, EAX);
142: else if (fixt == 2) AND32ItoR(EAX, 0xffff);
143: MOV32RtoM((u32)&psxRegs.CP2D.r[_Rt_], EAX);
144: // ADD32ItoR(ESP, 4);
145: resp+= 4;
146: }
147:
148: void gteSWC2();
149: static void recSWC2() {
150: // mem[Rs + Im] = Rt
151:
152: switch (_Rt_) {
153: case 29:
154: iFlushRegs();
155: MOV32ItoM((u32)&psxRegs.code, (u32)psxRegs.code);
156: CALLFunc ((u32)gteSWC2);
157: return;
158: }
159:
160: if (IsConst(_Rs_)) {
161: u32 addr = iRegs[_Rs_].k + _Imm_;
162: int t = addr >> 16;
163:
164: if ((t & 0x1fe0) == 0) {
165: MOV32MtoR(EAX, (u32)&psxRegs.CP2D.r[_Rt_]);
166: MOV32RtoM((u32)&psxM[addr & 0x1fffff], EAX);
167: return;
168: }
169: if (t == 0x1f80 && addr < 0x1f801000) {
170: MOV32MtoR(EAX, (u32)&psxRegs.CP2D.r[_Rt_]);
171: MOV32RtoM((u32)&psxH[addr & 0xfff], EAX);
172: return;
173: }
174: }
175:
176: PUSH32M ((u32)&psxRegs.CP2D.r[_Rt_]);
177: iPushOfB();
178: CALLFunc((u32)psxMemWrite32);
179: // ADD32ItoR(ESP, 8);
180: resp+= 8;
181: }
182:
183: static void recCFC2() {
184: // Rt = Cop2C->Rd
185: if (!_Rt_) return;
186:
187: iRegs[_Rt_].state = ST_UNK;
188: MOV32MtoR(EAX, (u32)&psxRegs.CP2C.r[_Rd_]);
189: MOV32RtoM((u32)&psxRegs.GPR.r[_Rt_], EAX);
190: }
191:
192: static void recCTC2() {
193: // Cop2C->Rd = Rt
194:
195: if (IsConst(_Rt_)) {
196: MOV32ItoM((u32)&psxRegs.CP2C.r[_Rd_], iRegs[_Rt_].k);
197: } else {
198: MOV32MtoR(EAX, (u32)&psxRegs.GPR.r[_Rt_]);
199: MOV32RtoM((u32)&psxRegs.CP2C.r[_Rd_], EAX);
200: }
201: }
202:
203: CP2_FUNCNC(RTPS);
204: CP2_FUNC(OP);
205: CP2_FUNCNC(NCLIP);
206: CP2_FUNCNC(DPCS);
207: CP2_FUNCNC(INTPL);
208: CP2_FUNC(MVMVA);
209: CP2_FUNCNC(NCDS);
210: CP2_FUNCNC(NCDT);
211: CP2_FUNCNC(CDP);
212: CP2_FUNCNC(NCCS);
213: CP2_FUNCNC(CC);
214: CP2_FUNCNC(NCS);
215: CP2_FUNCNC(NCT);
216: CP2_FUNC(SQR);
217: CP2_FUNCNC(DCPL);
218: CP2_FUNCNC(DPCT);
219: CP2_FUNCNC(AVSZ3);
220: CP2_FUNCNC(AVSZ4);
221: CP2_FUNCNC(RTPT);
222: CP2_FUNC(GPF);
223: CP2_FUNC(GPL);
224: CP2_FUNCNC(NCCT);
225:
226: #if 0
227:
228: #define gteVX0 ((s16*)psxRegs.CP2D.r)[0]
229: #define gteVY0 ((s16*)psxRegs.CP2D.r)[1]
230: #define gteVZ0 ((s16*)psxRegs.CP2D.r)[2]
231: #define gteVX1 ((s16*)psxRegs.CP2D.r)[4]
232: #define gteVY1 ((s16*)psxRegs.CP2D.r)[5]
233: #define gteVZ1 ((s16*)psxRegs.CP2D.r)[6]
234: #define gteVX2 ((s16*)psxRegs.CP2D.r)[8]
235: #define gteVY2 ((s16*)psxRegs.CP2D.r)[9]
236: #define gteVZ2 ((s16*)psxRegs.CP2D.r)[10]
237: #define gteRGB psxRegs.CP2D.r[6]
238: #define gteOTZ ((s16*)psxRegs.CP2D.r)[7*2]
239: #define gteIR0 ((s32*)psxRegs.CP2D.r)[8]
240: #define gteIR1 ((s32*)psxRegs.CP2D.r)[9]
241: #define gteIR2 ((s32*)psxRegs.CP2D.r)[10]
242: #define gteIR3 ((s32*)psxRegs.CP2D.r)[11]
243: #define gteSX0 ((s16*)psxRegs.CP2D.r)[12*2]
244: #define gteSY0 ((s16*)psxRegs.CP2D.r)[12*2+1]
245: #define gteSX1 ((s16*)psxRegs.CP2D.r)[13*2]
246: #define gteSY1 ((s16*)psxRegs.CP2D.r)[13*2+1]
247: #define gteSX2 ((s16*)psxRegs.CP2D.r)[14*2]
248: #define gteSY2 ((s16*)psxRegs.CP2D.r)[14*2+1]
249: #define gteSXP ((s16*)psxRegs.CP2D.r)[15*2]
250: #define gteSYP ((s16*)psxRegs.CP2D.r)[15*2+1]
251: #define gteSZx ((u16*)psxRegs.CP2D.r)[16*2]
252: #define gteSZ0 ((u16*)psxRegs.CP2D.r)[17*2]
253: #define gteSZ1 ((u16*)psxRegs.CP2D.r)[18*2]
254: #define gteSZ2 ((u16*)psxRegs.CP2D.r)[19*2]
255: #define gteRGB0 psxRegs.CP2D.r[20]
256: #define gteRGB1 psxRegs.CP2D.r[21]
257: #define gteRGB2 psxRegs.CP2D.r[22]
258: #define gteMAC0 psxRegs.CP2D.r[24]
259: #define gteMAC1 ((s32*)psxRegs.CP2D.r)[25]
260: #define gteMAC2 ((s32*)psxRegs.CP2D.r)[26]
261: #define gteMAC3 ((s32*)psxRegs.CP2D.r)[27]
262: #define gteIRGB psxRegs.CP2D.r[28]
263: #define gteORGB psxRegs.CP2D.r[29]
264: #define gteLZCS psxRegs.CP2D.r[30]
265: #define gteLZCR psxRegs.CP2D.r[31]
266:
267: #define gteR ((u8 *)psxRegs.CP2D.r)[6*4]
268: #define gteG ((u8 *)psxRegs.CP2D.r)[6*4+1]
269: #define gteB ((u8 *)psxRegs.CP2D.r)[6*4+2]
270: #define gteCODE ((u8 *)psxRegs.CP2D.r)[6*4+3]
271: #define gteC gteCODE
272:
273: #define gteR0 ((u8 *)psxRegs.CP2D.r)[20*4]
274: #define gteG0 ((u8 *)psxRegs.CP2D.r)[20*4+1]
275: #define gteB0 ((u8 *)psxRegs.CP2D.r)[20*4+2]
276: #define gteCODE0 ((u8 *)psxRegs.CP2D.r)[20*4+3]
277: #define gteC0 gteCODE0
278:
279: #define gteR1 ((u8 *)psxRegs.CP2D.r)[21*4]
280: #define gteG1 ((u8 *)psxRegs.CP2D.r)[21*4+1]
281: #define gteB1 ((u8 *)psxRegs.CP2D.r)[21*4+2]
282: #define gteCODE1 ((u8 *)psxRegs.CP2D.r)[21*4+3]
283: #define gteC1 gteCODE1
284:
285: #define gteR2 ((u8 *)psxRegs.CP2D.r)[22*4]
286: #define gteG2 ((u8 *)psxRegs.CP2D.r)[22*4+1]
287: #define gteB2 ((u8 *)psxRegs.CP2D.r)[22*4+2]
288: #define gteCODE2 ((u8 *)psxRegs.CP2D.r)[22*4+3]
289: #define gteC2 gteCODE2
290:
291:
292:
293: #define gteR11 ((s16*)psxRegs.CP2C.r)[0]
294: #define gteR12 ((s16*)psxRegs.CP2C.r)[1]
295: #define gteR13 ((s16*)psxRegs.CP2C.r)[2]
296: #define gteR21 ((s16*)psxRegs.CP2C.r)[3]
297: #define gteR22 ((s16*)psxRegs.CP2C.r)[4]
298: #define gteR23 ((s16*)psxRegs.CP2C.r)[5]
299: #define gteR31 ((s16*)psxRegs.CP2C.r)[6]
300: #define gteR32 ((s16*)psxRegs.CP2C.r)[7]
301: #define gteR33 ((s16*)psxRegs.CP2C.r)[8]
302: #define gteTRX ((s32*)psxRegs.CP2C.r)[5]
303: #define gteTRY ((s32*)psxRegs.CP2C.r)[6]
304: #define gteTRZ ((s32*)psxRegs.CP2C.r)[7]
305: #define gteL11 ((s16*)psxRegs.CP2C.r)[16]
306: #define gteL12 ((s16*)psxRegs.CP2C.r)[17]
307: #define gteL13 ((s16*)psxRegs.CP2C.r)[18]
308: #define gteL21 ((s16*)psxRegs.CP2C.r)[19]
309: #define gteL22 ((s16*)psxRegs.CP2C.r)[20]
310: #define gteL23 ((s16*)psxRegs.CP2C.r)[21]
311: #define gteL31 ((s16*)psxRegs.CP2C.r)[22]
312: #define gteL32 ((s16*)psxRegs.CP2C.r)[23]
313: #define gteL33 ((s16*)psxRegs.CP2C.r)[24]
314: #define gteRBK ((s32*)psxRegs.CP2C.r)[13]
315: #define gteGBK ((s32*)psxRegs.CP2C.r)[14]
316: #define gteBBK ((s32*)psxRegs.CP2C.r)[15]
317: #define gteLR1 ((s16*)psxRegs.CP2C.r)[32]
318: #define gteLR2 ((s16*)psxRegs.CP2C.r)[33]
319: #define gteLR3 ((s16*)psxRegs.CP2C.r)[34]
320: #define gteLG1 ((s16*)psxRegs.CP2C.r)[35]
321: #define gteLG2 ((s16*)psxRegs.CP2C.r)[36]
322: #define gteLG3 ((s16*)psxRegs.CP2C.r)[37]
323: #define gteLB1 ((s16*)psxRegs.CP2C.r)[38]
324: #define gteLB2 ((s16*)psxRegs.CP2C.r)[39]
325: #define gteLB3 ((s16*)psxRegs.CP2C.r)[40]
326: #define gteRFC ((s32*)psxRegs.CP2C.r)[21]
327: #define gteGFC ((s32*)psxRegs.CP2C.r)[22]
328: #define gteBFC ((s32*)psxRegs.CP2C.r)[23]
329: #define gteOFX ((s32*)psxRegs.CP2C.r)[24]
330: #define gteOFY ((s32*)psxRegs.CP2C.r)[25]
331: #define gteH ((u16*)psxRegs.CP2C.r)[52]
332: #define gteDQA ((s16*)psxRegs.CP2C.r)[54]
333: #define gteDQB ((s32*)psxRegs.CP2C.r)[28]
334: #define gteZSF3 ((s16*)psxRegs.CP2C.r)[58]
335: #define gteZSF4 ((s16*)psxRegs.CP2C.r)[60]
336: #define gteFLAG psxRegs.CP2C.r[31]
337:
338: //#define SUM_FLAG if(gteFLAG & 0x7F87E000) gteFLAG |= 0x80000000;
339:
340: #define SUM_FLAG() { \
341: TEST32ItoM((u32)>eFLAG, 0x7F87E000); \
342: j8Ptr[0] = JZ8(0); \
343: OR32ItoM((u32)>eFLAG, 0x80000000); \
344: \
345: x86SetJ8(j8Ptr[0]); \
346: }
347:
348: #define LIM32X8(reg, gteout, negv, posv, flagb) { \
349: CMP32ItoR(reg, negv); \
350: j8Ptr[0] = JL8(0); \
351: CMP32ItoR(reg, posv); \
352: j8Ptr[1] = JG8(0); \
353: \
354: MOV8RtoM((u32)>eout, reg); \
355: j8Ptr[2] = JMP8(0); \
356: \
357: x86SetJ8(j8Ptr[0]); \
358: MOV8ItoM((u32)>eout, negv); \
359: j8Ptr[3] = JMP8(0); \
360: \
361: x86SetJ8(j8Ptr[1]); \
362: MOV8ItoM((u32)>eout, posv); \
363: \
364: x86SetJ8(j8Ptr[3]); \
365: OR32ItoM((u32)>eFLAG, 1<<flagb); \
366: \
367: x86SetJ8(j8Ptr[2]); \
368: }
369:
370: #define _LIM_B1(reg, gteout) LIM32X8(reg, gteout, 0, 255, 21);
371: #define _LIM_B2(reg, gteout) LIM32X8(reg, gteout, 0, 255, 20);
372: #define _LIM_B3(reg, gteout) LIM32X8(reg, gteout, 0, 255, 19);
373:
374: #define MAC2IRn(reg, ir, flagb, negv, posv) { \
375: /* CMP32ItoR(reg, negv);*/ \
376: /* j8Ptr[0] = JL8(0); */\
377: /* CMP32ItoR(reg, posv);*/ \
378: /* j8Ptr[1] = JG8(0);*/ \
379: \
380: MOV32RtoM((u32)&ir, reg); \
381: /* j8Ptr[2] = JMP8(0);*/ \
382: \
383: /* x86SetJ8(j8Ptr[0]);*/ \
384: /* MOV32ItoM((u32)&ir, negv);*/ \
385: /* j8Ptr[3] = JMP8(0);*/ \
386: \
387: /* x86SetJ8(j8Ptr[1]);*/ \
388: /* MOV32ItoM((u32)&ir, posv);*/ \
389: \
390: /* x86SetJ8(j8Ptr[3]);*/ \
391: /* OR32ItoR((u32)>eFLAG, 1<<flagb);*/ \
392: \
393: /* x86SetJ8(j8Ptr[2]);*/ \
394: }
395:
396:
397:
398: #define gte_C11 gteLR1
399: #define gte_C12 gteLR2
400: #define gte_C13 gteLR3
401: #define gte_C21 gteLG1
402: #define gte_C22 gteLG2
403: #define gte_C23 gteLG3
404: #define gte_C31 gteLB1
405: #define gte_C32 gteLB2
406: #define gte_C33 gteLB3
407:
408:
409: #define _MVMVA_FUNC(vn, mx) { \
410: MOVSX32M16toR(EAX, (u32)&mx##vn##1); \
411: IMUL32R(EBX); \
412: /* j8Ptr[0] = JO8(0);*/ \
413: MOV32RtoR(ECX, EAX); \
414: \
415: MOVSX32M16toR(EAX, (u32)&mx##vn##2); \
416: IMUL32R(EDI); \
417: /* j8Ptr[1] = JO8(0);*/ \
418: ADD32RtoR(ECX, EAX); \
419: /* j8Ptr[2] = JO8(0);*/ \
420: \
421: MOVSX32M16toR(EAX, (u32)&mx##vn##3); \
422: IMUL32R(ESI); \
423: /* j8Ptr[3] = JO8(0);*/ \
424: ADD32RtoR(ECX, EAX); \
425: /* j8Ptr[4] = JO8(0);*/ \
426: }
427:
428: /* SSX = (_v0) * mx##11 + (_v1) * mx##12 + (_v2) * mx##13;
429: SSY = (_v0) * mx##21 + (_v1) * mx##22 + (_v2) * mx##23;
430: SSZ = (_v0) * mx##31 + (_v1) * mx##32 + (_v2) * mx##33; */
431:
432: #define _MVMVA_ADD(_vx, jn) { \
433: ADD32MtoR(ECX, (u32)&_vx); \
434: /* j8Ptr[jn] = JO8(0);*/ \
435: }
436: /* SSX+= gteRFC;
437: SSY+= gteGFC;
438: SSZ+= gteBFC;*/
439:
440: #define _MVMVA1(vn) { \
441: switch (psxRegs.code & 0x60000) { \
442: case 0x00000: /* R */ \
443: _MVMVA_FUNC(vn, gteR); break; \
444: case 0x20000: /* L */ \
445: _MVMVA_FUNC(vn, gteL); break; \
446: case 0x40000: /* C */ \
447: _MVMVA_FUNC(vn, gte_C); break; \
448: default: \
449: return; \
450: } \
451: }
452:
453: #define _MVMVA_LOAD(_v0, _v1, _v2) { \
454: MOVSX32M16toR(EBX, (u32)&_v0); \
455: MOVSX32M16toR(EDI, (u32)&_v1); \
456: MOVSX32M16toR(ESI, (u32)&_v2); \
457: }
458:
459: static void recMVMVA() {
460: int i;
461:
462: // SysPrintf("GTE_MVMVA %lx\n", psxRegs.code & 0x1ffffff);
463:
464: /* PUSH32R(ESI);
465: PUSH32R(EDI);
466: PUSH32R(EBX);
467: */
468: XOR32RtoR(EAX, EAX); /* gteFLAG = 0 */
469: MOV32RtoM((u32)>eFLAG, EAX);
470:
471: switch (psxRegs.code & 0x18000) {
472: case 0x00000: /* V0 */
473: _MVMVA_LOAD(gteVX0, gteVY0, gteVZ0); break;
474: case 0x08000: /* V1 */
475: _MVMVA_LOAD(gteVX1, gteVY1, gteVZ1); break;
476: case 0x10000: /* V2 */
477: _MVMVA_LOAD(gteVX2, gteVY2, gteVZ2); break;
478: case 0x18000: /* IR */
479: _MVMVA_LOAD(gteIR1, gteIR2, gteIR3); break;
480: }
481:
482: // MAC1
483: for (i=5; i<8; i++) j8Ptr[i] = 0;
484: _MVMVA1(1);
485:
486: if (psxRegs.code & 0x80000) {
487: SAR32ItoR(ECX, 12);
488: // SSX /= 4096.0; SSY /= 4096.0; SSZ /= 4096.0;
489: }
490:
491: switch (psxRegs.code & 0x6000) {
492: case 0x0000: // Add TR
493: _MVMVA_ADD(gteTRX, 5); break;
494: case 0x2000: // Add BK
495: _MVMVA_ADD(gteRBK, 6); break;
496: case 0x4000: // Add FC
497: _MVMVA_ADD(gteRFC, 7); break;
498: }
499: /*
500: j8Ptr[9] = JMP8(0);
501: for (i=0; i<5; i++) x86SetJ8(j8Ptr[i]);
502: for (i=5; i<8; i++) if (j8Ptr[i]) x86SetJ8(j8Ptr[i]);
503:
504: // TEST32ItoR(EDX, 0x80000000);
505: OR32ItoM((u32)>eFLAG, 1<<29);
506: x86SetJ8(j8Ptr[9]);*/
507: MOV32RtoM((u32)>eMAC1, ECX);
508:
509: if (psxRegs.code & 0x400) {
510: MAC2IRn(ECX, gteIR1, 24, 0, 32767);
511: } else {
512: MAC2IRn(ECX, gteIR1, 24, -32768, 32767);
513: }
514:
515: // MAC2
516: _MVMVA1(2);
517:
518: if (psxRegs.code & 0x80000) {
519: SAR32ItoR(ECX, 12);
520: // SSX /= 4096.0; SSY /= 4096.0; SSZ /= 4096.0;
521: }
522:
523: switch (psxRegs.code & 0x6000) {
524: case 0x0000: // Add TR
525: _MVMVA_ADD(gteTRY, 5); break;
526: case 0x2000: // Add BK
527: _MVMVA_ADD(gteGBK, 6); break;
528: case 0x4000: // Add FC
529: _MVMVA_ADD(gteGFC, 7); break;
530: }
531:
532: /* for (i=0; i<5; i++) x86SetJ8(j8Ptr[i]);
533: for (i=5; i<8; i++) if (j8Ptr[i]) x86SetJ8(j8Ptr[i]);*/
534: MOV32RtoM((u32)>eMAC2, ECX);
535:
536: if (psxRegs.code & 0x400) {
537: MAC2IRn(ECX, gteIR2, 23, 0, 32767);
538: } else {
539: MAC2IRn(ECX, gteIR2, 23, -32768, 32767);
540: }
541:
542: // MAC3
543: _MVMVA1(3);
544:
545: if (psxRegs.code & 0x80000) {
546: SAR32ItoR(ECX, 12);
547: // SSX /= 4096.0; SSY /= 4096.0; SSZ /= 4096.0;
548: }
549:
550: switch (psxRegs.code & 0x6000) {
551: case 0x0000: // Add TR
552: _MVMVA_ADD(gteTRZ, 5); break;
553: case 0x2000: // Add BK
554: _MVMVA_ADD(gteBBK, 6); break;
555: case 0x4000: // Add FC
556: _MVMVA_ADD(gteBFC, 7); break;
557: }
558:
559: /* for (i=0; i<5; i++) x86SetJ8(j8Ptr[i]);
560: for (i=5; i<8; i++) if (j8Ptr[i]) x86SetJ8(j8Ptr[i]);*/
561: MOV32RtoM((u32)>eMAC3, ECX);
562:
563: if (psxRegs.code & 0x400) {
564: MAC2IRn(ECX, gteIR3, 22, 0, 32767);
565: } else {
566: MAC2IRn(ECX, gteIR3, 22, -32768, 32767);
567: }
568: /* MAC2IR1()
569: else MAC2IR()*/
570:
571: // SUM_FLAG();
572:
573: /* POP32R(EBX);
574: POP32R(EDI);
575: POP32R(ESI);*/
576: }
577:
578: #if 0
579:
580: #define _GPF1(vn) { \
581: MOV32MtoR(EAX, (u32)>eIR##vn); \
582: IMUL32R(ECX); \
583: /* MOV32RtoR(ECX, EAX); */\
584: }
585:
586: static void recGPF() {
587: // SysPrintf("GTE_GPF %lx\n", psxRegs.code & 0x1ffffff);
588:
589: PUSH32R(EBX);
590:
591: XOR32RtoR(EBX, EBX); /* gteFLAG = 0 */
592:
593: /* gteMAC1 = NC_OVERFLOW1(gteIR0 * gteIR1);
594: gteMAC2 = NC_OVERFLOW2(gteIR0 * gteIR2);
595: gteMAC3 = NC_OVERFLOW3(gteIR0 * gteIR3);*/
596: MOV32MtoR(ECX, (u32)>eIR0);
597: // MAC1
598: _GPF1(1);
599:
600: if (psxRegs.code & 0x80000) {
601: SAR32ItoR(EAX, 12);
602: }
603: MAC2IRn(EAX, gteIR1, 24, -32768, 32767);
604: PUSH32R(EAX);
605:
606: // MAC2
607: _GPF1(2);
608:
609: if (psxRegs.code & 0x80000) {
610: SAR32ItoR(EAX, 12);
611: }
612: MAC2IRn(EAX, gteIR2, 23, -32768, 32767);
613: PUSH32R(EAX);
614:
615: // MAC3
616: _GPF1(3);
617:
618: if (psxRegs.code & 0x80000) {
619: SAR32ItoR(EAX, 12);
620: }
621: MAC2IRn(EAX, gteIR3, 22, -32768, 32767);
622: // MAC2IR();
623:
624: // gteRGB0 = gteRGB1;
625: // gteRGB1 = gteRGB2;
626: MOV32MtoR(EDX, (u32)>eRGB1);
627: MOV32MtoR(ECX, (u32)>eRGB2);
628: MOV32RtoM((u32)>eRGB0, EDX);
629: MOV32RtoM((u32)>eRGB1, ECX);
630:
631: POP32R(EDX);
632: POP32R(ECX);
633: SAR32ItoR(ECX, 4);
634: SAR32ItoR(EDX, 4);
635: SAR32ItoR(EAX, 4);
636:
637: _LIM_B1(ECX, gteR2);
638: _LIM_B2(EDX, gteG2);
639: _LIM_B3(EAX, gteB2);
640: MOV8MtoR(EAX, (u32)>eCODE);
641: MOV8RtoM((u32)>eCODE2, EAX);
642:
643: /* gteR2 = limB1(gteMAC1 / 16.0f);
644: gteG2 = limB2(gteMAC2 / 16.0f);
645: gteB2 = limB3(gteMAC3 / 16.0f); gteCODE2 = gteCODE;*/
646:
647: SUM_FLAG();
648: MOV32RtoM((u32)>eFLAG, EBX);
649:
650: // POP32R(EBX);
651: }
652: #endif
653: #endif
654: /* arch-tag: Matthew Dempsky Wed Oct 15 10:35:02 CST 2003 (ix86/iGte.h)
655: */
656:
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